//****************************************************************
// File Name  : count.v
// Author     : guangzu.he
// Date       :
// Description:
//
//****************************************************************
`timescale 1ns/1ns

module my_count(
        input   wire            clk_25m,
        input   wire            rst_n,
        input   wire            req,
        output  reg [15:0]          q
        );

reg        [15:0]count;
reg  d1 /* synthesis keep */;
reg  d2 /* synthesis keep */;
reg  d3 /* synthesis keep */;
always@(*)begin
    d2 <= ~d1;
    d3 <= ~d2;
    d1 <= ~d3;
end
always@(posedge clk_25m  or negedge rst_n)
    if(!rst_n)
        count <= 0;
    else
        count <= count + d3;

reg q1,q2,q3;

always@(posedge req  or posedge q3)
if(q3)
    q1 <= 0;
else
    q1 <= 1;

always@(posedge clk_25m or negedge rst_n)
if(!rst_n)
    q2 <= 0;
else
    q2 <= q1;

always@(posedge clk_25m or negedge rst_n)
if(!rst_n)
    q3 <= 0;
else
    q3 <= q2;

always@(posedge clk_25m  or negedge rst_n)
if(!rst_n)
    q <= 0;
else if(q3 && !q2)
    q <= count;



endmodule